SIMD_INSTRS=SIMD_INSTRS_0, THUMBCOPY_INSTRS=THUMBCOPY_INSTRS_0, SVC_INSTRS=SVC_INSTRS_0, SATURATE_INSTRS=SATURATE_INSTRS_0, TRUENOP_INSTRS=TRUENOP_INSTRS_0, TABBRANCH_INSTRS=TABBRANCH_INSTRS_0
Instruction Set Attributes Register 3
| SATURATE_INSTRS | Indicates the supported Saturate instructions 0 (SATURATE_INSTRS_0): None supported 1 (SATURATE_INSTRS_1): Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. |
| SIMD_INSTRS | Indicates the supported SIMD instructions 0 (SIMD_INSTRS_0): None supported, ARMv7-M unused. 1 (SIMD_INSTRS_1): Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. 3 (SIMD_INSTRS_3): As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. |
| SVC_INSTRS | Indicates the supported SVC instructions 0 (SVC_INSTRS_0): None supported, ARMv7-M unused. 1 (SVC_INSTRS_1): Adds support for the SVC instruction. |
| SYNCHPRIM_INSTRS | Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives |
| TABBRANCH_INSTRS | Indicates the supported Table Branch instructions 0 (TABBRANCH_INSTRS_0): None supported, ARMv7-M unused. 1 (TABBRANCH_INSTRS_1): Adds support for the TBB and TBH instructions. |
| THUMBCOPY_INSTRS | Indicates the supported non flag-setting MOV instructions 0 (THUMBCOPY_INSTRS_0): None supported, ARMv7-M unused. 1 (THUMBCOPY_INSTRS_1): Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. |
| TRUENOP_INSTRS | Indicates the supported non flag-setting MOV instructions 0 (TRUENOP_INSTRS_0): None supported, ARMv7-M unused. 1 (TRUENOP_INSTRS_1): Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. |